Get Analog Circuit Design: Smart Data Converters, Filters on PDF

By Bang-Sup Song (auth.), Arthur H. M. Roermund, Herman Casier, Michiel Steyaert (eds.)

ISBN-10: 9048130824

ISBN-13: 9789048130825

ISBN-10: 9048130832

ISBN-13: 9789048130832

Analog Circuit Design comprises the contribution of 18 tutorials of the 18th workshop on Advances in Analog Circuit layout. each one half discusses a particular to-date subject on new and necessary layout principles within the region of analog circuit layout. every one half is gifted by way of six specialists in that box and state-of-the-art details is shared and overviewed. This booklet is quantity 18 during this profitable sequence of Analog Circuit layout, offering worthy details and ideal overviews of

- shrewdpermanent info Converters,
chaired by means of Prof. Arthur van Roermund, Eindhoven collage of expertise

- Filters on Chip,
chaired through Herman Casier, AMI Semiconductor Fellow

- Multimode Transmitters,
chaired via Prof. Michiel Steyaert, Catholic college Leuven

Analog Circuit layout is a vital reference resource for analog circuit designers and researchers wishing to maintain abreast with the most recent improvement within the box. the educational insurance additionally makes it appropriate to be used in a complicated layout course.

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Extra info for Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters

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N LNA LO individual channels multiple channels ADC input 1 3 n 4 2 0 fs /2 input frequency Fig. 1 Typical multi-channel receiver users demands an even higher SFDR of 100 dB. The ADC’s resolution should then be 14 b or higher such that the errors and spurs arising due to the quantization are at least 10 dB lower than the required maximum level. The blocks in Fig. 1 can be partitioned over a number of dies or integrated on a single die. Integration on a single die brings a significant reduction of the total system cost.

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2126–2138, Dec. 2004. 14. J. -C. -Y. -K. 960–969, Apr. 2005. 15. -C. -M. -T. 1047–1056, May 2005. 16. S. -S. 463–474, Mar. 2007. 17. E. Siragusa, I. 2126–2138, Dec. 2004. 18. J. McNeill, M. Coln, B. Larivee, “A split-ADC architecture for deterministic digital background calibration of a 16b 1 MS/s ADC,” Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 276–598, Feb. 2005. 19. Y. W. Tsang, B. R. 38–46, Jan. 2004. 20. I. A. 1626–1637, Jul. 2008. 21. B. 2040–2050, Dec. 2003.

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Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters by Bang-Sup Song (auth.), Arthur H. M. Roermund, Herman Casier, Michiel Steyaert (eds.)


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